1. Field of the Invention
The present invention relates generally to the field of data transmission and, more specifically, to managing conflicts on a shared L2 data bus.
2. Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as “L2 cache”). The L2 cache is a large on-chip memory that temporarily stores data being used by the various clients. This data may be retrieved from or written to many partitions of an external memory (each such partition referred to herein as a “DRAM”). A memory controller (referred to herein as “DRAM controller”) manages the flow of data being transmitted to or retrieved from the DRAM.
Typically, data being transmitted between the L2 cache and the DRAM is transmitted over an L2 bus. At any given clock cycle, the L2 bus maybe used to transmit write data from the L2 cache to one DRAM or read data from one DRAM to the L2 cache. Because processing of read and write commands received from the L2 cache to the different DRAMs happens concurrently, at a given clock cycle, more than one DRAM may need to access the L2 bus to transmit read or write data. In such a situation, a conflict occurs on the L2 bus.
More specifically, a read-read conflict occurs when two or more DRAMs need to transmit read data to the L2 cache at the same clock cycle. A write-write conflict occurs when two or more DRAMs need to retrieve write data from the L2 cache at the same clock cycle. Lastly, a read-write conflict occurs when one DRAM needs to transmit read data to the L2 cache while another DRAM needs to retrieve write data from the L2 cache. Further, read data associated with a read command is usually returned from the DRAM several clock cycles after the transmission of the read command to that DRAM, and write data associated with a write command is transmitted to the DRAM with the actual write command. Because write data needs to be retrieved from the L2 cache and read data needs to be returned to the L2 cache, a read-write conflict may occur on the L2 bus when the DRAM switches from processing read commands to processing write commands.
If these different conflicts on the L2 bus are not properly managed, the read and write commands may be stalled, resulting in a decrease of overall system performance.
As the foregoing illustrates, what is needed in the art is an effective mechanism for managing conflicts on the L2 bus when processing read and write commands between the L2 cache and the various external DRAMs.